MOSFET series resistance extraction at cryogenic temperatures

Abstract A series resistance extraction method proposed recently, which uses multiple drain current versus gate voltage curves at varied voltages, was applied to bulk CMOS devices low temperatures down 4 K. moderate reduction of compared with 300 K found. Horizontal field dependence mobility significantly changed temperature, taken into account during the extraction. Anomalous non-linear observed only for p-channel FETs, suggesting need careful source/drain overlap design temperature operations.